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ltc2497 1 2497fb for more information www.linear.com/ltc2497 r source ( ) 1 +fs error (ppm) C20 0 20 1k 100k 2497 ta01b C40C60 C80 10 100 10k 40 60 80 v cc = 5v v ref = 5v v in + = 3.75v v in C = 1.25v f o = gnd t a = 25c c in = 1mf 16-bit 8-/16-channel ds adc with easy drive input current cancellation and i 2 c interface typical application features applications description the lt c ? 2497 is a 16-channel (eight differential), 16-bit, no latency ds tm adc with easy drive technology and a 2-wire, i 2 c interface. the patented sampling scheme eliminates dynamic input current errors and the shortcom - ings of on-chip buffering through automatic cancellation of differential input current. this allows large external sour ce impedances and rail-to-rail input signals to be directly digitized while maintaining exceptional dc accuracy. the ltc2497 includes an integrated oscillator. this device can be configured to measure an external signal from com - binations of 16 analog input channels operating in single- ended or differential modes. it automatically rejects line frequencies of 50hz and 60hz simultaneously. the l tc2497 allows a wide, common mode input range (0v to v cc ), independent of the reference voltage. any combination of single-ended or differential inputs can be selected and the first conversion, after a new channel is selected, is valid. access to the multiplexer output enables optional external amplifiers to be shared between all analog inputs and auto calibration continuously removes their associated offset and drift. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and no latency ? and easy drive are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. easy drive data acquisition system n up to eight differential or 16 single-ended inputs n easy drive tm technology enables rail-to-rail inputs with zero differential input current n directly digitizes high impedance sensors with full accuracy n 2-wire i 2 c interface with 27 addresses plus one global address for synchronization n 600nv rms noise (0.02lsb transition noise) n gnd to v cc input/reference common mode range n simultaneous 50hz/60hz rejection n 2ppm inl, no missing codes n 1ppm offset and 15ppm full-scale error n no latency: digital filter settles in a single cycle, even after a new channel is selected n single supply, 2.7v to 5.5v operation (0.8mw) n internal oscillator n tiny 5mm 7mm qfn package n direct sensor digitizer n direct temperature measurement n instrumentation n industrial process control +fs error vs r source at in + and in ? scl sda f o ref + v cc muxout/adcin muxout/ adcin 2.7v to 5.5v 10f 1.7k com ref ? 16-bit ? adc with easy drive 16-channel mux in + in ? 2497 ta01 2-wirei 2 c interface ch0ch1 ?? ? ?? ? ch7ch8 ch15 0.1f osc downloaded from: http:///
ltc2497 2 2497fb for more information www.linear.com/ltc2497 absolute maximum ratings supply voltage (v cc ) ................................... ?0.3v to 6v analog input voltage (ch0-ch15, com) ..................... ?0.3v to (v cc + 0.3v) ref + , ref ? ................................ ?0.3v to (v cc + 0.3v) adcinn, adcinp, muxoutp muxoutn .............. ?0.3v to (v cc + 0.3v) digital input voltage ...................... ?0.3v to (v cc + 0.3v) digital output voltage ................... ?0.3v to (v cc + 0.3v) operating temperature range ltc2497c ................................................. 0oc to 70oc ltc2497i ............................................. ?40oc to 85oc storage temperature range ................... ?65oc to 150oc (notes 1, 2) pin configuration 13 14 15 16 top view 39 uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 gnd scl sda gnd nc gnd com ch0ch1 ch2 ch3 ch4 gndref ? ref + v cc muxoutn adcinnadcinp muxoutp ch15 ch14 ch13 ch12 ca2ca1 ca0 f o gndgnd gnd ch5ch6 ch7 ch8 ch9 ch10ch11 23 22 21 20 9 10 11 12 t jmax = 125c, ja = 34c/w exposed pad (pin 39) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range ltc2497cuhf#pbf ltc2497cuhf#trpbf 2497 38-lead (5mm 7mm) plastic qfn 0c to 70c ltc2497iuhf#pbf ltc2497iuhf#trpbf 2497 38-lead (5mm 7mm) plastic qfn ?40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www .linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
ltc2497 3 2497fb for more information www.linear.com/ltc2497 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (notes 3, 4) parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , ?fs v in +fs (note 5) 16 bits integral nonlinearity 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v (note 6) 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v (note 6) l 2 1 20 ppm of v ref ppm of v ref offset error 2.5v v ref v cc , gnd in + = in ? v cc (note 13) l 0.5 2.5 v offset error drift 2.5v v ref v cc , gnd in + = in ? v cc 10 nv/c positive full-scale error 2.5v v ref v cc , in + = 0.75v ref , in ? = 0.25v ref l 32 ppm of v ref positive full-scale error drift 2.5v v ref v cc , in + = 0.75v ref , in ? = 0.25v ref 0.1 ppm of v ref /c negative full-scale error 2.5v v ref v cc , in + = 0.25v ref , in ? = 0.75v ref l 32 ppm of v ref negative full-scale error drift 2.5v v ref v cc , in + = 0.25v ref , in ? = 0.75v ref 0.1 ppm of v ref /c total unadjusted error 5v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v 15 15 15 ppm of v ref ppm of v ref ppm of v ref output noise 2.7v < v cc < 5.5v, 2.5v v ref v cc , gnd in + = in ? v cc (note 12) 0.6 v rms converter characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) parameter conditions min typ max units input common mode rejection dc 2.5v v ref v cc , gnd in + = in ? v cc (note 5) l 140 db input normal mode rejection 50hz/60hz 2% 2.5v v ref v cc , gnd in + = in ? v cc (notes 5, 9) l 87 db reference common mode rejection dc 2.5v v ref v cc , gnd in + = in ? v cc (note 5) l 120 140 db power supply rejection dc v ref = 2.5v, in + = in ? = gnd 120 db power supply rejection, 50hz 2% v ref = 2.5v, in + = in ? = gnd (notes 7, 9) 120 db power supply rejection, 60hz 2% v ref = 2.5v, in + = in ? = gnd (notes 8, 9) 120 db analog input and reference the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) symbol parameter conditions min typ max units in + absolute/common mode in + voltage (in + corresponds to the selected positive input channel) gnd ? 0.3v v cc + 0.3v v in ? absolute/common mode in ? voltage (in ? corresponds to the selected negative input channel or com) gnd ? 0.3v v cc + 0.3v v v in input voltage range (in + ? in ? ) differential/single-ended l ?fs +fs v fs full scale of the input (in + ? in ? ) differential/single-ended l 0.5v ref v lsb least significant bit of the output code l fs/2 16 ref + absolute/common mode ref + voltage l 0.1 v cc v ref ? absolute/common mode ref ? voltage l gnd ref + ? 0.1v v v ref reference voltage range (ref + ? ref ? ) l 0.1 v cc v cs(in + ) in + sampling capacitance 11 pf cs(in ? ) in ? sampling capacitance 11 pf cs(v ref ) v ref sampling capacitance 11 pf i dc_leak(in + ) in + dc leakage current sleep mode, in + = gnd l ?10 1 10 na downloaded from: http:///
ltc2497 4 2497fb for more information www.linear.com/ltc2497 i 2 c inputs and digital outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) symbol parameter conditions min typ max units v ih high level input voltage l 0.7v cc v v il low level input voltage l 0.3v cc v v iha high level input voltage for address pins ca0, ca1, ca2, and pin f o l 0.95v cc v v ila low level input voltage for address pins ca0, ca1, ca2 l 0.05v cc v r inh resistance from ca0, ca1, ca2 to v cc to set chip address bit to 1 l 10 k w r inl resistance from ca0, ca1, ca2 to gnd to set chip address bit to 0 l 10 k w r inf resistance from ca0, ca1, ca2 to gnd or v cc to set chip address bit to float l 2 m w i i digital input current l ?10 10 a v hys hysteresis of schmidt trigger inputs (note 5) l 0.05v cc v v ol low level output voltage (sda) i = 3ma l 0.4 v t of output fall time v ih(min) to v il(max) bus load c b 10pf to 400pf (note 14) l 20 + 0.1c b 250 ns i in input leakage 0.1v cc v in v cc l 1 a c cax external capacitative load on chip address pins (ca0, ca1, ca2) for valid float l 10 pf power requirements the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion current (note 11) sleep mode (note 11) l l 160 1 275 2 a a analog input and reference the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) i dc_leak(in ? ) in ? dc leakage current sleep mode, in ? = gnd l ?10 1 10 na i dc_ leak(ref + ) ref + dc leakage current sleep mode, ref + = v cc l ?100 1 100 na i dc_ leak(ref ? ) ref ? dc leakage current sleep mode, ref ? = gnd l ?100 1 100 na t open mux break-before-make 50 ns qirr mux off isolation v in = 2v p-p dc to 1.8mhz 120 db downloaded from: http:///
ltc2497 5 2497fb for more information www.linear.com/ltc2497 symbol parameter conditions min typ max units f eosc external oscillator frequency range (note 16) l 10 1000 khz t heo external oscillator high period l 0.125 100 s t leo external oscillator low period l 0.125 100 s t conv conversion time internal oscillator external oscillator (note 10) l 144.1 146.9 41036/f eosc (in khz) 149.9 ms ms digital inputs and digital outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) symbol parameter conditions min typ max units f scl scl clock frequency l 0 400 khz t hd(sda) hold time (repeated) start condition l 0.6 s t low low period of the scl pin l 1.3 s t high high period of the scl pin l 0.6 s t su(sta) set-up time for a repeated start condition l 0.6 s t hd(dat) data hold time l 0 0.9 s t su(dat) data set-up time l 100 ns t r rise time for sda signals (note 14) l 20 + 0.1c b 300 ns t f fall time for sda signals (note 14) l 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 s i 2 c timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3, 15) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd. note 3: v cc = 2.7v to 5.5v unless otherwise specified. v refcm = v ref /2, f s = 0.5v ref v in = in + ? in ? , v in(cm) = (in + ? in ? )/2, where in + and in ? are the selected input channels. note 4: use internal conversion clock or external conversion clock source with f eosc = 307.2khz unless otherwise specified. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: f eosc = 256khz 2% (external oscillator). note 8: f eosc = 307.2khz 2% (external oscillator). note 9: simultaneous 50hz/60hz (internal oscillator) or f eosc = 280khz 2% (external oscillator).note 10: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 11: the converter uses its internal oscillator. note 12: the output noise includes the contribution of the internal calibration operations.note 13: guaranteed by design and test correlation. note 14: c b = capacitance of one bus line in pf (10pf c b 400pf). note 15: all values refer to v ih(min) and v il(max) levels. note 16: refer to applications information section for performance versus data rate graphs. downloaded from: http:///
ltc2497 6 2497fb for more information www.linear.com/ltc2497 input voltage (v) ?3 inl (ppm of v ref ) ?1 1 3 ?2 0 2 ?1.5 ?0.5 0.5 1.5 2497 g01 2.5 ?2 ?2.5 ?1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 85c ?45c 25c input voltage (v) ?3 inl (ppm of v ref ) ?1 1 3 ?2 0 2 ?0.75 ?0.25 0.25 0.75 2497 g02 1.25 ?1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v f o = gnd ?45c, 25c, 85c input voltage (v) ?3 inl (ppm of v ref ) ?1 1 3 ?2 0 2 ?0.75 ?0.25 0.25 0.75 2497 g03 1.25 ?1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd ?45c, 25c, 85c input voltage (v) ?12 tue (ppm of v ref ) ?4 4 12 ?8 0 8 ?1.5 ?0.5 0.5 1.5 2497 g04 2.5 ?2 ?2.5 ?1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 85c 25c ?45c input voltage (v) ?12 tue (ppm of v ref ) ?4 4 12 ?8 0 8 ?0.75 ?0.25 0.25 0.75 2497 g05 1.25 ?1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v f o = gnd 85c 25c ?45c input voltage (v) ?12 tue (ppm of v ref ) ?4 4 12 ?8 0 8 ?0.75 ?0.25 0.25 0.75 2497 g06 1.25 ?1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd 85c 25c ?45c typical performance characteristics integral nonlinearity (v cc = 5v, v ref = 5v) integral nonlinearity (v cc = 5v, v ref = 2.5v) integral nonlinearity (v cc = 2.7v, v ref = 2.5v) total unadjusted error (v cc = 5v, v ref = 5v) total unadjusted error (v cc = 5v, v ref = 2.5v) total unadjusted error (v cc = 2.7v, v ref = 2.5v) downloaded from: http:///
ltc2497 7 2497fb for more information www.linear.com/ltc2497 v ref (v) 0 ?0.3 offset error (ppm of v ref ) ?0.2 ?0.1 0 0.1 0.2 0.3 1 2 3 4 2497 g10 5 v cc = 5v ref ? = gnd v in = 0v v in(cm) = gnd t a = 25c f o = gnd temperature (c) ?45 ?30 300 frequency (khz) 304 310 ?15 30 45 2497 g11 302 308 306 15 0 60 75 90 v cc = 4.1v v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd v cc (v) 2.7 300 frequency (khz) 302 304 306 308 310 3.0 3.5 4.0 4.5 2497 g12 5.0 5.5 v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c typical performance characteristics offset error vs v ref on-chip oscillator frequency vs temperature on-chip oscillator frequency vs v cc v in(cm) (v) ?1 offset error (ppm of v ref ) 0.1 0.2 0.3 2 4 2497 g07 0 ?0.1 0 1 3 5 6 ?0.2 ?0.3 v cc = 5v v ref = 5v v in = 0v t a = 25c f o = gnd temperature (c) ?45 ?0.3 offset error (ppm of v ref ) ?0.2 0 0.1 0.2 ?15 15 30 90 2497 g08 ?0.1 ?30 0 45 60 75 0.3 v cc = 5v v ref = 5v v in = 0v f o = gnd v cc (v) 2.7 offset error (ppm of v ref ) 0.1 0.2 0.3 3.9 4.7 2497 g09 0 ?0.1 3.1 3.5 4.3 5.1 5.5 ?0.2 ?0.3 ref + = 2.5v ref ? = gnd v in = 0v v in(cm) = gnd t a = 25c f o = gnd offset error vs v in(cm) offset error vs temperature offset error vs v cc downloaded from: http:///
ltc2497 8 2497fb for more information www.linear.com/ltc2497 typical performance characteristics frequency at v cc (hz) 1 0 ?20?40 ?60 ?80 ?100?120 ?140 1k 100k 2497 g13 10 100 10k 1m rejection (db) v cc = 4.1v dc v ref = 2.5v in + = gnd in ? = gnd f o = gnd t a = 25c frequency at v cc (hz) 0 ?140 rejection (db) ?120 ?80 ?60 ?40 0 20 100 140 2497 g14 ?100 ?20 80 180 220 200 40 60 120 160 v cc = 4.1v dc 1.4v v ref = 2.5v in + = gnd in ? = gnd f o = gnd t a = 25c frequency at v cc (hz) 30600 ?60 ?40 0 30750 2497 g15 ?80 ?100 30650 30700 30800 ?120?140 ?20 rejection (db) v cc = 4.1v dc 0.7v v ref = 2.5v in + = gnd in ? = gnd f o = gnd t a = 25c temperature (c) ?45 100 conversion current (a) 120 160 180 200 ?15 15 30 90 2497 g16 140 ?30 0 45 60 75 v cc = 5v v cc = 2.7v f o = gnd scl = 0sda = 1 temperature (c) ?45 0 sleep mode current (a) 0.2 0.6 0.8 1.0 2.0 1.4 ?15 15 30 90 2497 g17 0.4 1.6 1.81.2 ?30 0 45 60 75 v cc = 5v v cc = 2.7v f o = gnd scl = 0sda = 1 psrr vs frequency at v cc psrr vs frequency at v cc psrr vs frequency at v cc conversion current vs temperature sleep mode current vs temperature conversion current vs output data rate output data rate (readings/sec) 0 supply current (a) 500450 400 350 300 250 200 150 100 2497 g18 10 30 20 v cc = 5v v cc = 3v v ref = v cc in + = gnd in ? = gnd scl = 0sda = 1 t a = 25c downloaded from: http:///
ltc2497 9 2497fb for more information www.linear.com/ltc2497 gnd (pins 1, 4, 6, 31, 32, 33, 34): ground. multiple ground pins internally connected for optimum ground cur - rent flow and v cc decoupling. connect each one of these pins to a common ground plane through a low impedance connection. all seven pins must be connected to ground for proper operation. scl (pin 2): serial clock pin of the i 2 c interface. the ltc2497 can only act as a slave and the scl pin only accepts an external serial clock. data is shifted into the sda pin on the rising edges of the scl clock and output through the sda pin on the falling edges of the scl clock. sda (pin 3): bidirectional serial data line of the i 2 c inter - face. in the transmitter mode (read), the conversion result is output through the sda pin, while in the receiver mode (write), the device channel select bits are input through the sda pin. the pin is high impedance during the data input mode and is an open drain output (requires an appropri - ate pull-up device to v cc ) during the data output mode. nc (pin 5): no connect. this pin can be left floating or tied to gnd.com (pin 7): the common negative input (in ? ) for all single-ended multiplexer configurations. the voltage on ch0-ch15 and com pins can have any value between gnd ? 0.3v to v cc + 0.3v. within these limits, the two selected inputs (in + and in ? ) provide a bipolar input range (v in = in + ? in ? ) from C0.5 ? v ref to 0.5 ? v ref . outside this input range, the converter produces unique over-range and under-range output codes. ch0 to ch15 (pin 8-pin 23): analog inputs. may be pro - grammed for single-ended or differential mode.muxoutp (pin 24): positive multiplexer output. connect to the input of external buffer/amplifier or short directly to adcinp . adcinp (pin 25): positive adc input. connect to the output of a buffer/amplifier driven by muxoutp or short directly to muxoutp. adcinn (pin 26): negative adc input. connect to the output of a buffer/amplifier driven by muxoutn or short directly to muxoutn muxoutn (pin 27): negative multiplexer output. con - nect to the input of an external buffer/amplifier or short directly to adcinn. v cc (pin 28): positive supply voltage. bypass to gnd with a 10f tantalum capacitor in parallel with a 0.1f ceramic capacitor as close to the part as possible. ref + , ref ? (pin 29, pin 30): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , remains more positive than the negative reference input, ref ? , by at least 0.1v. the differential voltage (v ref = ref + ? ref ? ) sets the full-scale range for all input channels. f o (pin 35): frequency control pin. digital input that controls the internal conversion clock rate. when f o is connected to gnd, the converter uses its internal oscil - lator running at 307.2khz. the conversion clock may also be overridden by driving the f o pin with an external clock in order to change the output rate and the digital filter rejection null. ca0, ca1, ca2 (pins 36, 37, 38): chip address control pins. these pins are configured as a three-state (low, high, floating) address control bits for the device i 2 c address.gnd (exposed pad pin 39): ground. this pin is ground and must be soldered to the pcb ground plane. for pro - totyping purposes, this pin may remain floating. pin functions downloaded from: http:///
ltc2497 10 2497fb for more information www.linear.com/ltc2497 functional block diagram autocalibration and control differential 3rd order ? modulator decimating fir address internal oscillator i 2 c 2-wire interface gnd v cc ch0ch1 ?? ? ch15 com mux sda ref + ref ? adcinn muxoutn adcinp muxoutp scl f o (int/ext) 2497 bd + ? downloaded from: http:///
ltc2497 11 2497fb for more information www.linear.com/ltc2497 converter operation converter operation cycle the ltc2497 is a multichannel, low power, delta-sigma analog-to-digital converter with a 2-wire, i 2 c interface. its operation is made up of four states (see figure 1). the converter operating cycle begins with the conversion, followed by the sleep state and ends with the data input/ output cycle. applications information figure 1. state transition table conversion sleep 2497 f01 yes no acknowledge yes no stop or read 24 bits data output/input power-on reset default input channel: in + = ch0, in ? = ch1 the device will not acknowledge an external request dur - ing the conversion state. after a conversion is finished, the device is ready to accept a read/write request. once the ltc2497 is addressed for a read operation, the device begins outputting the conversion result under the control of the serial clock (scl). there is no latency in the conver - sion result. the data output is 24 bits long and contains a 16-bit plus sign conversion result. data is updated on the falling edges of scl allowing the user to reliably latch data on the rising edge of scl. a new conversion is initiated by a stop condition following a valid write operation or an incomplete read operation. the conversion automatically begins at the conclusion of a complete read cycle (all 24 bits read out of the device). ease of use the l tc2497 data output has no latency, filter settling delay, or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog inputs is straightforward. each conversion, immediately following a newly selected input is valid and accurate to the full specifications of the device. the ltc2497 automatically performs offset and full-scale calibration every conversion cycle independent of the input channel selected. this calibration is transparent to the user and has no effect on the operation cycle described above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, sup - ply voltage variation, input channel, and temperature drift.easy drive input current cancellation the ltc2497 combines a high precision, delta-sigma adc with an automatic, differential, input current cancellation f ront end. a proprietary front end passive sampling network transparently removes the differential input current. this enables external rc networks and high impedance sen - sors to directly interface to the ltc2497 without external amplifiers. the remaining common mode input current is eliminated by either balancing the differential input im - pedances or setting the common mode input equal to the common mode reference (see the automatic differential initially, at power-up, the ltc2497 performs a conver - sion. once the conversion is complete, the device enters the sleep state. in the sleep state, power consumption is reduced by two orders of magnitude. the part remains in the sleep state as long it is not addressed for a read/ write operation. the conversion result is held indefinitely in a static shift register while the part is in the sleep state. downloaded from: http:///
ltc2497 12 2497fb for more information www.linear.com/ltc2497 input current cancellation section). this unique architec - ture does not require on-chip buffers, thereby enabling signals to swing beyond ground and v cc . moreover, the cancellation does not interfere with the transparent offset and full-scale auto-calibration and the absolute accuracy (full scale + offset + linearity + drift) is maintained even with external rc networks. power-up sequence the ltc2497 automatically enters an internal reset state when the power supply voltage v cc drops below approxi - mately 2.0v. this feature guarantees the integrity of the conversion result and input channel selection. when v cc rises above this threshold, the converter creates an internal power-on-reset (por) signal with a duration of approximately 4ms. the por signal clears all internal registers. the conversion immediately following a por cycle is performed on the input channel in + = ch0, in ? = ch1. the first conversion following a por cycle is accurate within the specification of the device if the power supply voltage is restored to (2.7v to 5.5v) before the end of the por interval. a new input channel can be programmed into the device during this first data input/output cycle. reference voltage range this converter accepts a truly differential, external reference voltage. the absolute/common mode voltage range for ref + and ref ? pins covers the entire operating range of the device (gnd to v cc ). for correct converter operation, v ref must be positive (ref + > ref ? ). the ltc2497 differential reference input range is 0.1v to v cc . for the simplest operation, ref + can be shorted to v cc and ref ? can be shorted to gnd. the converter out - put noise is determined by the thermal noise of the front end circuits. since the transition noise is well below 1lsb (0.02lsb), a decrease in reference voltage will proportion - ally improve the converter resolution and improve inl. input voltage range the ltc2497 input measurement range is C0.5 ? v ref to +0.5 ? v ref in both differential and single-ended configura - tions as shown in figure 28. highest linearity is achieved with fully differential drive and a constant common-mode voltage (figure 28b). other drive schemes may incur an inl error of approximately 50ppm. this error can be calibrated out using a three point calibration and a second-order curve fit. the analog inputs are truly differential with an absolute, common mode range for the ch0-ch15 and com input pins extending from gnd ? 0.3v to v cc + 0.3v. within these limits, the ltc2497 converts the bipolar differen - tial input signal v in = in + ? in ? (where in + and in ? are the selected input channels), from C fs = C 0.5 ? v ref to + fs = 0.5 ? v ref where v ref = ref + - ref ? . outside this range, the converter indicates the overrange or the under - range condition using distinct output codes (see table 1). signals applied to the input (ch0-ch15, com) may extend 300mv below ground and above v cc . in order to limit any fault current due to input esd leakage current, resistors of up to 5k may be added in series with the input. the ef - fect of series resistance on the converter accuracy can be evaluated from the curves presented in the input current/ reference current sections. in addition, series resistors will introduce a temperature dependent error due to input leakage current. a 1na input leakage current will develop a 1ppm offset error on a 5k resistor if v ref = 5v. this error has a very strong temperature dependency. muxout/adcin the outputs of the multiplexer (muxoutp/muxoutn) and the inputs to the adc (adcinp/adcinn) can be used to perform input signal conditioning on any of the selected input channels or simply shorted together for direct digitization. if an external amplifier is used, the ltc2497 automatically calibrates both the offset and drift of this circuit and the easy drive sampling scheme enables a wide variety of amplifiers to be used. applications information downloaded from: http:///
ltc2497 13 2497fb for more information www.linear.com/ltc2497 in order to achieve optimum performance, if an external amplifier is not used, short these pins directly together (adcinp to muxoutp and adcinn to muxoutn) and minimize their capacitance to ground. i 2 c interface the ltc2497 communicates through an i 2 c interface. the i 2 c interface is a 2-wire open-drain interface supporting multiple devices and multiple masters on a single bus. the connected devices can only pull the data line (sda) low and can never drive it high. sda is required to be exter - nally connected to the supply through a pull-up resistor. when the data line is not being driven, it is high. data on the i 2 c bus can be transferred at rates up to 100kbits/s in the standard mode and up to 400kbits/s in the fast mode. each device on the i 2 c bus is recognized by a unique address stored in that device and can operate either as a transmitter or receiver, depending on the function of the device. in addition to transmitters and receivers, devices can also be considered as masters or slaves when perform - ing data transfers. a master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. devices addressed by the master are considered a slave. the ltc2497 can only be addressed as a slave. once ad - dressed, it can receive channel selection bits or transmit the last conversion result. the serial clock line, scl, is always an input to the ltc2497 and the serial data line sda is bidirectional. the device supports the standard mode and the fast mode for data transfer speeds up to 400kbits/s. figure 2 shows the definition of the i 2 c timing. the start and stop conditions a start (s) condition is generated by transitioning sda from high to low while scl is high. the bus is considered to be busy after the start condition. when the data transfer is finished, a stop (p) condition is generated by transitioning s da from low to high while scl is high. the bus is free after a stop is generated. start and stop conditions are always generated by the master. when the bus is in use, it stays busy if a repeated start (sr) is generated instead of a stop condition. the repeated start timing is functionally identical to the start and is used for writing and reading from the device before the initiation of a new conversion. data transferring after the start condition, the i 2 c bus is busy and data transfer can begin between the master and the addressed slave. data is transferred over the bus in groups of nine bits, one byte followed by one acknowledge (ack) bit. the master releases the sda line during the ninth scl clock cycle. the slave device can issue an ack by pulling sda low or issue a not acknowledge (nak) by leaving the sda line high impedance (the external pull-up resistor will hold the line high). change of data only occurs while the clock line (scl) is low. data format after a start condition, the master sends a 7-bit address followed by a read/write (r/w) bit. the r/w bit is 1 for a read request and 0 for a write request. if the 7-bit address matches the hard wired, ltc2497?s address (one of 27 sda scl s sr p s t hd(sda) t hd(dat) t su(sta) t su(sto) t su(dat) t low t hd(sda) t sp t buf t r t f t r t f t high 2497 f02 figure 2. definition of timing for fast/standard mode devices on the i 2 c bus applications information downloaded from: http:///
ltc2497 14 2497fb for more information www.linear.com/ltc2497 pin-selectable addresses) the device is selected. when the device is addressed during the conversion state, it will not acknowledge r/w requests and will issue a nak by leaving the sda line high. if the conversion is complete, the ltc2497 issues an ack by pulling the sda line low. the ltc2497 has two registers. the output register (24 bits long) contains the last conversion result. the input register (8 bits long) sets the input channel. data output format the output register contains the last conversion result. after each conversion is completed, the device automati - cally enters the sleep state where the supply current is reduced to 1a. when the ltc2497 is addressed for a read operation, it acknowledges (by pulling sda low) and acts as a transmitter. the master/receiver can read up to three bytes from the ltc2497. after a complete read operation (3 bytes), a new conversion is initiated. the device will nak subsequent read operations while a conversion is being performed. the data output stream is 24 bits long and is shifted out on the falling edges of scl (see figure 3a). the first bit is the conversion result sign bit (sig) (see tables 1 and 2). this bit is high if v in 0 and low if v in < 0 (where v in corresponds to the selected input signal in + ? in ? ). the table 1. output data format differential input voltage v in * bit 23 sig bit 22 msb bit 21 bit 20 bit 19 ? bit 6 lsb bits 5-0 always 0 v in * fs** 1 1 0 0 0 ? 0 000000 fs** ? 1lsb 1 0 1 1 1 ? 1 000000 0.5 ? fs** 1 0 1 0 0 ? 0 000000 0.5 ? fs** C 1lsb 1 0 0 1 1 ? 1 000000 0 1 0 0 0 0 ? 0 000000 ?1lsb 0 1 1 1 1 ? 1 000000 C0.5 ? fs** 0 1 1 0 0 ? 0 000000 C0.5 ? fs** C 1lsb 0 1 0 1 1 ? 1 000000 ?fs** 0 1 0 0 0 ? 0 000000 v in * < ?fs** 0 0 1 1 1 ? 1 000000 *the differential input voltage v in = in + ? in ? . **the full-scale voltage fs = 0.5 ? v ref . second bit is the most significant bit (msb) of the result. the first two bits (sig and msb) can be used to indicate over and under range conditions (see table 2). if both bits are high, the differential input voltage is equal to or above +fs. if both bits are set low, the input voltage is below ?fs. the function of these bits is summarized in table 2. the 16 bits following the msb bit are the conversion result in binary two?s complement format. the remaining six bits are always 0. as long as the voltage on the selected input channels (in + and in ? ) remains between ?0.3v and v cc + 0.3v (absolute maximum operating range) a conversion result is gener - ated for any differential input voltage v in from ?fs = ?0.5 ? v ref to +fs = 0.5 ? v ref . for differential input voltages greater than +fs, the conversion result is clamped to the value corresponding to +fs. for differential input volt - ages below ?fs, the conversion result is clamped to the value ?fs ? 1lsb. table 2. ltc2497 status bits input range bit 23 sig bit 22 msb v in fs 1 1 0v v in < fs 1 0 ?fs v in < 0v 0 1 v in < ?fs 0 0 applications information downloaded from: http:///
ltc2497 15 2497fb for more information www.linear.com/ltc2497 input data format the ltc2497 serial input is 8 bits long and is written into the device in one 8-bit word. sgl, odd, a2, a1, a0 are used to select the input channel. after power-up, the device initiates an internal reset cycle which sets the input channel to ch0-ch1 (in + = ch0, in ? = ch1). the first conversion automatically begins at power- up using this default input channel. once the conversion is complete, a new channel may be written into the device. the first three bits of the input word consist of two pre - amble bits and one enable bit. these three bits are used to enable the input channel selection. v alid settings for these three bits are 000, 100, and 101. other combinations should be avoided. if the first three bits are 000 or 100, the following data is ignored (don?t care) and the previously selected input channel remains valid for the next conversion. if the first three bits shifted into the device are 101, then the next five bits select the input channel for the next conversion cycle (see table 3). the first input bit (sgl) following the 101 sequence de - termines if the input selection is differential (sgl = 0) or single-ended (sgl = 1). for sgl = 0, two adjacent channels can be selected to form a differential input. for sgl = 1, one of 16 channels is selected as the positive input. the negative input is com for all single-ended operations. the remaining four bits (odd, a2, a1, a0) determine which channel(s) is/are selected and the polarity (for a differential input). figure 3a. timing diagram for reading from the ltc2497 applications information sleep data output ack by ltc2497 ack by master always low start by master nak by master lsb r msb sgn d15 7 ? ? 8 9 1 2 9 1 2 3 4 5 6 7 8 9 1 7-bit address 2497 f03a sclsda sleep data input ack by ltc2497 ack by ltc2497 nak by ltc2497 start by master sgl odd w 0 1 sclsda en a2 a1 a0 7 ? 8 9 1 2 9 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 1 7-bit address 2497 f03b x x x x x x x x figure 3b. timing diagram for writing to the ltc2497 downloaded from: http:///
ltc2497 16 2497fb for more information www.linear.com/ltc2497 table 3. channel selection mux address channel selection sgl odd/ sign a2 a1 a0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 com *0 0 0 0 0 in + in ? 0 0 0 0 1 in + in ? 0 0 0 1 0 in + in ? 0 0 0 1 1 in + in ? 0 0 1 0 0 in + in ? 0 0 1 0 1 in + in ? 0 0 1 1 0 in + in ? 0 0 1 1 1 in + in ? 0 1 0 0 0 in ? in + 0 1 0 0 1 in ? in + 0 1 0 1 0 in ? in + 0 1 0 1 1 in ? in + 0 1 1 0 0 in ? in + 0 1 1 0 1 in ? in + 0 1 1 1 0 in ? in + 0 1 1 1 1 in ? in + 1 0 0 0 0 in + in ? 1 0 0 0 1 in + in ? 1 0 0 1 0 in + in ? 1 0 0 1 1 in + in ? 1 0 1 0 0 in + in ? 1 0 1 0 1 in + in ? 1 0 1 1 0 in + in ? 1 0 1 1 1 in + in ? 1 1 0 0 0 in + in ? 1 1 0 0 1 in + in ? 1 1 0 1 0 in + in ? 1 1 0 1 1 in + in ? 1 1 1 0 0 in + in ? 1 1 1 0 1 in + in ? 1 1 1 1 0 in + in ? 1 1 1 1 1 in + in ? *default at power up applications information downloaded from: http:///
ltc2497 17 2497fb for more information www.linear.com/ltc2497 initiating a new conversion when the ltc2497 finishes a conversion, it automatically enters the sleep state. once in the sleep state, the device is ready for a read operation. after the device acknowledges a read request, the device exits the sleep state and enters the data output state. the data output state concludes and the ltc2497 starts a new conversion once a stop condi - tion is issued by the master or all 24 bits of data are read out of the device. during the data read cycle, a stop command may be issued by the master controller in order to start a new conversion and abort the data transfer . this stop command must be issued during the ninth clock cycle of a byte read when the bus is free (the ack/nak cycle). ltc2497 address the ltc2497 has three address pins (ca0, ca1, ca2). each may be tied high, low, or left floating enabling one of 27 possible addresses (see table 4). in addition to the configurable addresses listed in table 4, the ltc2497 also contains a global address (1110111) which may be used for synchronizing multiple ltc2497s or other ltc24xx delta-sigma i 2 c devices, (see synchroniz - ing multiple ltc2497s with global address call section). operation sequence the ltc2497 acts as a transmitter or receiver , as shown in figure 4. the device may be programmed to select an input channel, differential or single-ended mode, and channel polarity. continuous read in applications where the input channel does not need to change for each cycle, the conversion can be continuously performed and read without a write cycle (see figure 5). the input channel remains unchanged from the last value written into the device. if the device has not been written to since power up, the channel selection is set to the de - fault value of ch0 = in + , ch1 = in ? . at the end of a read operation, a new conversion automatically begins. at the table 4. address assignment ca2 ca1 ca0 address low low low 0010100 low low high 0010110 low low float 0010101 low high low 0100110 low high high 0110100 low high float 0100111 low float low 0010111 low float high 0100101 low float float 0100100 high low low 1010110 high low high 1100100 high low float 1010111 high high low 1110100 high high high 1110110 high high float 1110101 high float low 1100101 high float high 1100111 high float float 1100110 float low low 0110101 float low high 0110111 float low float 0110110 float high low 1000111 float high high 1010101 float high float 1010100 float float low 1000100 float float high 1000110 float float float 1000101 conclusion of the conversion cycle, the next result may be read using the method described above. if the conver - sion cycle is not concluded and a valid address selects the device, the l tc2497 generates a nak signal indicating the conversion cycle is in progress.continuous read/write once the conversion cycle is concluded, the ltc2497 can be written to and then read from using the repeated start (sr) command. applications information downloaded from: http:///
ltc2497 18 2497fb for more information www.linear.com/ltc2497 s ack d at a sr d at a transferring p sleep d at a input/output conversion conversion 7-bit address r/w 2497 f04 7-bit address conversion conversion conversion sleep sleep d at a output d at a output 7-bit address s s r r ack ack read read p p 2497 f05 7-bit address conversion conversion address sleep data output d at a input 7-bit address s r w ack ack write sr p read 2497 f06 7-bit address conversion conversion sleep d at a input s w ack write (optional) p 2497 f07 figure 4. conversion sequence figure 5. consecutive reading with the same input/configuration figure 6. write, read, start conversion figure 7. start a new conversion without reading old conversion result applications information figure 6 shows a cycle which begins with a data write, a repeated start, followed by a read and concluded with a stop command. the following conversion begins after all 24 bits are read out of the device or after a stop com - mand . the following conversion will be performed using the newly programmed data. discarding a conversion result and initiating a new conversion with optional write at the conclusion of a conversion cycle, a write cycle can be initiated. once the write cycle is acknowledged, a stop command will start a new conversion. if a new input channel is required, this data can be written into the device and a stop command will initiate the next conversion (see figure 7). downloaded from: http:///
ltc2497 19 2497fb for more information www.linear.com/ltc2497 global address scl sda ltc2497 ltc2497 ltc2497 ? all ltc2497s in sleep conversion of all ltc2497 s data input s w ack write (optional) p 2497 f08 synchronizing multiple ltc2497s with a global address call in applications where several ltc2497s (or other i 2 c delta- sigma adcs from linear technology corporation) are used on the same i 2 c bus, all converters can be synchronized through the use of a global address call. prior to issuing the global address call, all converters must have completed a conversion cycle. the master then issues a start, followed by the global address 1110111, and a write request. all converters will be selected and acknowledge the request. the master then sends a write byte (optional) followed by the stop command. this will update the channel selection (optional) and simultaneously initiate a start of conversion for all delta-sigma adcs on the bus (see figure 8). in order to synchronize multiple converters without changing the channel, a stop may be issued after acknowledgement of the global write command. global read commands are not allowed and the converters will nak a global read request. figure 8. synchronize multiple ltc2497s with a global address call driving the input and reference the input and reference pins of the ltc2497 are connected directly to a switched capacitor network. depending on the relationship between the differential input voltage and the differential reference voltage, these capacitors are switched between these four pins. each time a capacitor is switched between two of these pins, a small amount of charge is transferred. a simplified equivalent circuit is shown in figure 9. when using the ltc2497?s internal oscillator, the input capacitor array is switched at 123khz. the effect of the charge transfer depends on the circuitry driving the input/ reference pins. if the total external rc time constant is less than 580ns the errors introduced by the sampling process are negligible since complete settling occurs. applications information downloaded from: http:///
ltc2497 20 2497fb for more information www.linear.com/ltc2497 in + in ? 10k internal switch network 10k c eq 12 f 10k i in C ref + i ref + i in + i ref C 2497 f09 switching frequencyf sw = 123khz internal oscillator f sw = 0.4 ? f eosc external oscillator ref C 10k 100 input multiplexer external connection 100 muxoutp adcinp external connection muxoutn adcinn typically, the reference inputs are driven from a low impedance source. in this case, complete settling occurs even with large external bypass capacitors. the inputs (ch0-ch15, com), on the other hand, are typically driven from larger source resistances. sour ce resistances up to 10k may interface directly to the ltc2497 and settle completely; however, the addition of external capacitors at the input terminals in order to filter unwanted noise (anti-aliasing) results in incomplete settling. the ltc2497 offers two methods of removing these errors. the first is an automatic differential input current cancellation (easy drive) and the second is the insertion of an external buffer between the muxout and adcin pins, thus isolating the input switching from the source resistance.automatic differential input current cancellation in applications where the sensor output impedance is low (up to 10k w with no external bypass capacitor or up to 500 w with 0.001f bypass), complete settling of the input occurs. in this case, no errors are introduced and direct digitization is possible. figure 9. equivalent analog input circuit for many applications, the sensor output impedance combined with external input bypass capacitors produces rc time constants much greater than the 580ns required for 1ppm accuracy. for example, a 10k w bridge driving a 0.1f capacitor has a time constant an order of magnitude greater than the required maximum. the ltc2497 uses a proprietary switching algorithm that forces the average differential input current to zero independent of external settling errors. this allows direct digitization of high impedance sensors without the need for buffers. the switching algorithm forces the average input current on the positive input (i in + ) to be equal to the average input current on the negative input (i in ? ). over the complete conversion cycle, the average differential input current (i in + ? i in ? ) is zero. while the differential input current is zero, the common mode input current (i in + + i in ? )/2 is proportional to the difference between the common mode input voltage (v in(cm) ) and the common mode reference voltage (v ref(cm) ). applications information ii ni in vv r avg avg in cm re fc m eq + () = () = ? ? ? () () . 05 i ir ef vv v r avg re fr ef cm in cm + () + () 15 05 .? .? () () e eq in re fe q re f re fc m v vr wh er e vr ef re f v ? ? : ( 2 =? +? )) ? , = ?? ?? ?? ?? =? +? +? + re fr ef vi ni nw here in an in 2 d di na re th es elected in pu tc hann els v in in cm ? + = () ? ?i n ? ?? ?? ?? ?? =w 2 r 2.98 mi nte rna lo sci llator r eqe eq 12 eo sc 0.833 10 /f exte rna lo sci llator =? () downloaded from: http:///
ltc2497 21 2497fb for more information www.linear.com/ltc2497 in applications where the input common mode voltage is equal to the reference common mode voltage, as in the case of a balanced bridge, both the differential and com - mon mode input current are zero. the accuracy of the converter is not compromised by settling errors. in applications where the input common mode voltage is constant but different from the reference common mode voltage, the differential input current remains zero while the common mode input current is proportional to the difference between v in(cm) and v ref(cm) . for a reference common mode voltage of 2.5v and an input common mode of 1.5v, the common mode input current is ap - proximately 0.74a. this common mode input current does not degrade the accuracy if the source impedances tied to in + and in ? are matched. mismatches in source impedance lead to a fixed offset error but do not effect the linearity or full-scale reading. a 1% mismatch in a 1k source resistance leads to a 74v shift in offset voltage. in applications where the common mode input voltage varies as a function of the input signal level (single-ended type sensors), the common mode input current varies proportionally with input voltage. for the case of balanced input impedances, the common mode input current effects are rejected by the large cmrr of the ltc2497, leading to little degradation in accuracy. mismatches in source impedances lead to gain errors proportional to the dif - ference between the common mode input and common mode reference. 1% mismatches in 1k sour ce resistances lead to gain errors on the order of 15ppm. based on the stability of the internal sampling capacitors and the ac - curacy of the internal oscillator , a one-time calibration will remove this error. in addition to the input sampling current, the input esd protection diodes have a temperature dependent leakage current. this current, nominally 1na (10na max), results in a small offset shift. a 1k sour ce resistance will create a 1v typical and a 10v maximum offset voltage. automatic offset calibration of external buffers/ amplifiers in addition to the easy drive input current cancellation, the ltc2497 allows an external amplifier to be inserted between the multiplexer output and the adc input (see figure 10). this is useful in applications where balanced source impedances are not possible. one pair of external buffers/amplifiers can be shared between all 17 analog inputs. the ltc2497 performs an internal offset calibration every conversion cycle in order to remove the offset and drift of the adc. this calibration is performed through a figure 10. external buffers provide high impedance inputs and amplifier offsets are automatically cancelled. ? + ? + 1/2 ltc6078 1/2 ltc6078 1 2 3 5 6 7 ? adc with easy drive inputs input mux muxoutpmuxoutn 17 2497 f10 ltc2497 analog inputs scl sda 0.1f 1k 1k 0.1f applications information downloaded from: http:///
ltc2497 22 2497fb for more information www.linear.com/ltc2497 combination of front end switching and digital process - ing. since the external amplifier is placed between the multiplexer and the adc, it is inside this correction loop. this results in automatic offset correction and offset drift removal of the external amplifier. the ltc6078 is an excellent amplifier for this function. it operates with supply voltages as low as 2.7v and its noise level is 18nv/ hz . the easy drive input technology of the ltc2497 enables an rc network to be added directly to the output of the ltc6078. the capacitor reduces the magnitude of the current spikes seen at the input to the adc and the resistor isolates the capacitor load from the op-amp output enabling stable operation. the ltc6078 can also be biased at supply rails beyond those used by the ltc2497. this allows the external sensor to swing rail- to-rail (?0.3v to v cc + 0.3v) without the need of external level shift circuitry. reference current similar to the analog inputs, the ltc2497 samples the differential reference pins (ref + and ref ? ) transferring small amounts of charge to and from these pins, thus producing a dynamic reference current. if incomplete set - tling occurs (as a function the reference source resistance and reference bypass capacitance) linearity and gain errors are introduced. for relatively small values of external reference capacitance (c ref < 1nf), the voltage on the sampling capacitor settles for reference impedances of many k w (if c ref = 100pf up to 10k w will not degrade the performance) (see figures 11 and 12).in cases where large bypass capacitors are required on the reference inputs (c ref > 0.01f), full-scale and linear - ity errors are proportional to the value of the reference resistance. every ohm of reference resistance produces a full-scale error of approximately 0.5ppm (while operat - figure 11. +fs error vs r source at v ref (small c ref ) figure 12. ?fs error vs r source at v ref (small c ref ) applications information r source ( ) 0 +fs error (ppm) 50 70 90 10k 2497 f11 3010 40 60 8020 0 C10 10 100 1k 100k v cc = 5v v ref = 5v v in + = 3.75v v in C = 1.25v f o = gnd t a = 25c c ref = 0.01f c ref = 0.001f c ref = 100pf c ref = 0pf r source ( ) 0 Cfs error (ppm) C30 C10 10 10k 2497 f12 C50C70 C40 C20 0 C60C80 C90 10 100 1k 100k v cc = 5v v ref = 5v v in + = 1.25v v in C = 3.75v f o = gnd t a = 25c c ref = 0.01f c ref = 0.001f c ref = 100pf c ref = 0pf downloaded from: http:///
ltc2497 23 2497fb for more information www.linear.com/ltc2497 figure 15. inl vs differential input voltage and reference source resistance for c ref > 1f ing with the internal oscillator) (see figures 13 and 14). if the input common mode voltage is equal to the reference common mode voltage, a linearity error of approximately 0.67ppm per 100 w of reference resistance results (see figure 15). in applications where the input and reference common mode voltages are different, the errors increase. a 1v difference in between common mode input and common mode reference results in a 6.7ppm inl error for every 100 w of reference resistance. in addition to the reference sampling charge, the reference esd protection diodes have a temperature dependent leak - age current. this leakage current, nominally 1na (10na max) results in a small, gain error . a 100 w reference resistance will create a 0.5v full-scale error. applications information v in /v ref ?0.5 inl (ppm of v ref ) 2 6 10 0.3 2497 f15 ?2?6 0 4 8 ?4?8 ?10 ?0.3 ?0.1 0.1 0.5 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c c ref = 10f r = 1k r = 100 r = 500 figure 13. +fs error vs r source at v ref (large c ref ) figure 14. ?fs error vs r source at v ref (large c ref ) r source ( ) 0 +fs error (ppm) 300 400 500 800 2497 f13 200 100 0 200 400 600 1000 v cc = 5v v ref = 5v v in + = 3.75v v in C = 1.25v f o = gnd t a = 25c c ref = 1 f, 10 f c ref = 0.1 f c ref = 0.01 f r source ( ) 0 Cfs error (ppm) C200 C100 0 800 2497 f14 C300 C400 C500 200 400 600 1000 v cc = 5v v ref = 5v v in + = 1.25v v in C = 3.75v f o = gnd t a = 25c c ref = 1 f, 10 f c ref = 0.1 f c ref = 0.01 f normal mode rejection and anti-aliasing one of the advantages delta-sigma adcs offer over conventional adcs is on-chip digital filtering. combined with a large oversample ratio, the ltc2497 significantly simplifies anti-aliasing filter requirements. additionally, the input current cancellation feature allows external low pass filtering without degrading the dc performance of the device. the sinc 4 digital filter provides excellent normal mode rejection at all frequencies except dc and integer multiples of the modulator sampling frequency (f s ). the modulator sampling frequency is f s = 15,360hz while operating with its internal oscillator and f s = f eosc /20 when operating with an external oscillator of frequency f eosc . downloaded from: http:///
ltc2497 24 2497fb for more information www.linear.com/ltc2497 input signal frequency (hz) input normal mode rejection (db) 2497 f16 0 ?10?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100?110 ?120 f n 0 2f n 3f n 4f n 5f n 6f n 7f n 8f n f n = f eosc/5120 input signal frequency (hz) 250f n 252f n 254f n 256f n 258f n 260f n 262f n input normal mode rejection (db) 2497 f17 0 ?10?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100?110 ?120 f n = f eosc/5120 figure 17. input normal mode rejection at f s = 256 ? f n figure 16. input normal mode rejection at dc when using the internal oscillator, the ltc2497 is designed to reject line frequencies. as shown in figure 16, rejection nulls occur at multiples of frequency f n , where f n = 55hz for simultaneous 50hz/60hz rejection. multiples of the modulator sampling rate (f s = f n ? 256) only reject noise to 15db (see figure 17); if noise sources are present at these frequencies anti-aliasing will reduce their effects. the user can expect to achieve this level of performance us - ing the internal oscillator, as shown in figure 18. measured values of normal mode rejection are shown superimposed over the theoretical values. traditional high order delta-sigma modulators suffer from potential instabilities at large input signal levels. the proprietar y architecture used for the ltc2497 third order modulator resolves this problem and guarantees stability with input signals 150% of full scale. in many industrial applications, it is not uncommon to have microvolt level signals superimposed over unwanted error sources with several volts if peak-to-peak noise. figure 19 shows mea - surement results for the rejection of a 7.5v peak-to-peak noise source (150% of full scale) applied to the l tc2497. this curve shows that the rejection performance is main - tained even in extremely noisy environments.output data rate when using its internal oscillator, the ltc2497 produces up to 7.5 samples per second (sps) with a notch frequency of 60hz. the actual output data rate depends upon the length of the sleep and data output cycles which are controlled by the user and can be made insignificantly short. when operating with an external conversion clock (f o connected to an external oscillator), the ltc2497 output data rate can be increased. the duration of the conversion cycle is 41036/f eosc . if f eosc = 307.2khz, the converter behaves as if the internal oscillator is used. applications information downloaded from: http:///
ltc2497 25 2497fb for more information www.linear.com/ltc2497 input frequency (hz) 0 20 40 60 80 100 120 140 160 180 200 220 normal mode rejection (db) 2497 f18 0 ?20?40 ?60 ?80 ?100?120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25c measured datacalculated data input frequency (hz) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 normal mode rejection (db) 2497 f19 0 ?20?40 ?60 ?80 ?100?120 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) an increase in f eosc over the nominal 307.2khz will trans- late into a proportional increase in the maximum output data rate (up to a maximum of 100sps). the increase in output rate leads to degradation in offset, full-scale error, and effective resolution as well as a shift in frequency rejection. a change in f eosc results in a proportional change in the internal notch position. this leads to reduced differential mode rejection of line frequencies. the common mode rejection of line frequencies remains unchanged, thus fully differential input signals with a high degree of symmetry on both the in + and in ? pins will continue to reject line frequency noise. an increase in f eosc also increases the effective dynamic input and reference current. external rc networks will continue to have zero differential input current, but the time required for complete settling (580ns for f eosc = 307.2khz) is reduced, proportionally. once the external oscillator frequency is increased above 1mhz (a more than 3x increase in output rate) the ef - fectiveness of internal auto calibration circuits begins to degrade. this results in larger offset errors, full-scale errors, and decreased resolution, as shown in figures 20 to 27. figure 18. input normal mode rejection vs input frequency with input perturbation of 100% (50hz/60hz notch) figure 19. measure input normal mode rejection vs input frequency with input perturbation of 150% (60hz notch) applications information downloaded from: http:///
ltc2497 26 2497fb for more information www.linear.com/ltc2497 figure 20. offset error vs output data rate and temperature figure 21. +fs error vs output data rate and temperature figure 22.?fs error vs output data rate and temperature figure 23. resolution (noise rms 1lsb) vs output data rate and temperature figure 24. resolution (inl max 1lsb) vs output data rate and temperature figure 26. resolution (noise rms 1lsb) vs output data rate and reference voltage figure 27. resolution (inl max 1lsb) vs output data rate and reference voltage figure 25. offset error vs output data rate and reference voltage applications information output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 10 2497 f23 14 20 30 v in(cm) = v ref(cm) v cc = v ref = 5v v in = 0v f o = ext clock res = log 2 (v ref /noise rms ) t a = 25c, 85c output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 10 14 20 30 t a = 25c, 85c v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock res = log 2 (v ref /inl max ) 2497 f24 output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 10 2497 f26 14 20 30 v in(cm) = v ref(cm) v in = 0v f o = ext clock t a = 25c res = log 2 (v ref /noise rms ) v cc = 5v, v ref = 2.5v, 5v output data rate (readings/sec) ?10 offset error (ppm of v ref ) 10 30 50 0 20 40 20 2497 f20 30 0 10 v in(cm) = v ref(cm) v cc = v ref = 5v v in = 0v f o = ext clock t a = 85c t a = 25c output data rate (readings/sec) 0 0 +fs error (ppm of v ref ) 500 1500 2000 2500 3500 10 2497 f21 1000 3000 20 30 v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock t a = 85c t a = 25c output data rate (readings/sec) 0 ?10 offset error (ppm of v ref ) ?5 5 10 20 10 2497 f25 0 15 20 30 v in(cm) = v ref(cm) v in = 0v f o = ext clock t a = 25c v cc = 5v, v ref = 2.5v v cc = v ref = 5v output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 10 14 20 30 v cc = 5v, v ref = 2.5v v cc = v ref = 5v v in(cm) = v ref(cm) v in = 0v ref ? = gnd f o = ext clock t a = 25c res = log 2 (v ref /inl max ) 2497 f27 output data rate (readings/sec) 0 ?3500 ?fs error (ppm of v ref ) ?3000 ?2000 ?1500 ?1000 0 10 2497 f22 ?2500 ?500 20 30 v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock t a = 85c t a = 25c downloaded from: http:///
ltc2497 27 2497fb for more information www.linear.com/ltc2497 applications information figure 28. input range v cc + 0.3v gnd gnd gnd ?0.3v gnd ?0.3v ?0.3v (a) arbitrary (b) fully differential (d) pseudo-differential unipolar in? or com grounded (c) pseudo differential bipolar in? or com biased v ref 2 v ref 2 v ref 2 v ref 2 v ref 2 ?v ref 2 ?v ref 2 ?v ref 2 selected in + ch selected in ? ch or com v cc v cc v cc v cc 2497 f28 downloaded from: http:///
ltc2497 28 2497fb for more information www.linear.com/ltc2497 package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 5.00 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1top mark (see note 6) 37 12 38 bottom view?exposed pad 5.50 ref 5.15 0.10 7.00 0.10 0.75 0.05 r = 0.125 typ r = 0.10 typ 0.25 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 ? 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 0.10 0.70 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 0.05 5.50 0.05 5.15 0.05 6.10 0.05 7.50 0.05 0.25 0.05 packageoutline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notchr = 0.30 typ or 0.35 45 chamfer uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c) downloaded from: http:///
ltc2497 29 2497fb for more information www.linear.com/ltc2497 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 7/10 revised typical application drawing revised parameter for v iha in i 2 c inputs and digital outputs section 14 b 11/14 clarified performance vs frequency, reduced external oscillator max frequency to 1mhz clarified input voltage range 5, 8, 26 3, 12, 27 downloaded from: http:///
ltc2497 30 2497fb for more information www.linear.com/ltc2497 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 ? linear technology corporation 2006 lt 1114 rev b ? printed in usa (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2497 related parts typical application part number description comments lt ? 1236a-5 precision bandgap reference, 5v 0.05% max initial accuracy, 5ppm/c drift lt1460 micropower series reference 0.075% max initial accuracy, 10ppm/c max drift lt1790 micropower sot-23 low dropout reference family 0.05% max initial accuracy, 10ppm/c max drift ltc2400 24-bit, no latency ds adc in so-8 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200a ltc2410 24-bit, no latency ds adc with differential inputs 0.8v rms noise, 2ppm inl ltc2411/ltc2411-1 24-bit, no latency ds adcs with differential inputs in msop 1.45v rms noise, 2ppm inl, simultaneous 50hz/60hz rejection (ltc2411-1) ltc2413 24-bit, no latency ds adc with differential inputs simultaneous 50hz/60hz rejection, 800nv rms noise ltc2440 high speed, low noise 24-bit ds adc 3.5khz output rate, 200nv rms noise, 24.6 enobs ltc2442 24-bit, high speed, 4-channel/2-channel ds adc with integrated amplifier 8khz output rate, 220nv rms noise, simultaneous 50hz/60hz rejection ltc2449 24-bit, high speed, 8-channel/16-channel ds adc 8khz output rate, 200nv rms noise, simultaneous 50hz/60hz rejection ltc2480/ltc2482/ ltc2484 16-bit/24-bit ds adcs with easy drive inputs, 600nv rms noise, programmable gain, and temperature sensor pin-compatible with 16-bit and 24-bit versions ltc2481/ltc2483/ ltc2485 16-bit/24-bit ds adcs with easy drive inputs, 600nv rms noise, i 2 c interface, programmable gain, and temperature sensor pin-compatible with 16-bit and 24-bit versions ltc2496 16-bit 8-/16-channel ds adc with easy drive inputs and spi interface pin-compatible with ltc2498/l tc2449 ltc2498 24-bit 8-/16-channel ds adc with easy drive inputs and spi interface pin-compatible with ltc2496/ltc2449 ltc2499 24-bit 8-/16-channel ds adc with easy drive inputs and i 2 c interface, and temperature sensor pin-compatible with ltc2497 ? + ? + 1/2 ltc60781/2 ltc6078 1 2 3 5 6 7 ? adc with easy drive inputs input mux muxoutpmuxoutn 17 2497 ta02 ltc2497 analog inputs scl sda 1k 1k 0.1f 0.1f external buffers provide high impedance inputs and amplifier offsets are automatically cancelled downloaded from: http:///

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